Faster Born Probability Estimation Via Gate Merging And Frame Optimisation

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Nikolaos Koukoulekidis¹, Hyukjoon Kwon^1,2, Hyejung H. Jee³, David Jennings^1,4, and M. S. Kim¹

¹Department of Physics, Imperial College London, London SW7 2AZ, UK
²Korea Institute for Advanced Study, Seoul, 02455, Korea
³Department of Computing, Imperial College London, London SW7 2AZ, UK
⁴School of Physics and Astronomy, University of Leeds, Leeds, LS2 9JT, UK

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Abstract

Outcome probability estimation via classical methods is an important task for validating quantum computing devices. Outcome probabilities of any quantum circuit can be estimated using Monte Carlo sampling, where the amount of negativity present in the circuit frame representation quantifies the overhead on the number of samples required to achieve a certain precision. In this paper, we propose two classical sub-routines: circuit gate merging and frame optimisation, which optimise the circuit representation to reduce the sampling overhead. We show that the runtimes of both sub-routines scale polynomially in circuit size and gate depth. Our methods are applicable to general circuits, regardless of generating gate sets, qudit dimensions and the chosen frame representations for the circuit components. We numerically demonstrate that our methods provide improved scaling in the negativity overhead for all tested cases of random circuits with Clifford+$T$ and Haar-random gates, and that the performance of our methods compares favourably with prior quasi-probability simulators as the number of non-Clifford gates increases.

Featured image: Sketch of our routine on a toy circuit. The first step (a) $rightarrow$ (b) is gate merging, here implemented with $n = 2$. Gates that share input and output wires merge in the schematic way depicted in the figure. The second step (b) $rightarrow$ (c) is frame optimisation, here implemented with $ell= 2$ in a block $B$ comprising the three merged gates. The optimisation results into updated frames $G_4, G_7$, while the remaining frames that connect the block $B$ to the rest of the circuit components are left unchanged at this optimisation cycle.

Popular summary

Quantum computers are expected to provide significant speed-ups compared to classical computing for certain tasks. Determining the set of computational tasks that can be accelerated by the use of quantum computers is a notoriously hard question. A natural approach towards carving out this set consists of studying how well classical computers can simulate these tasks. A large family of such classical simulators relies on representing the tasks as stochastic processes that propagate an input state probabilistically. Quantum tasks contain negative probabilities that in principle require exponential runtimes to simulate classically. In this work, we introduce an efficient optimisation to the classical simulation strategy which works by minimising the negative probabilities that arise during the process. Our results are of practical significance as they provide a faster way to simulate quantum computers, while on a fundamental level, they probe the extent to which negative probabilities are an indicator of non-classical physics.

► BibTeX data

@article{Koukoulekidis2022fasterborn, doi = {10.22331/q-2022-10-13-838}, url = {https://doi.org/10.22331/q-2022-10-13-838}, title = {Faster {B}orn probability estimation via gate merging and frame optimisation}, author = {Koukoulekidis, Nikolaos and Kwon, Hyukjoon and Jee, Hyejung H. and Jennings, David and Kim, M. S.}, journal = {{Quantum}}, issn = {2521-327X}, publisher = {{Verein zur F{“{o}}rderung des Open Access Publizierens in den Quantenwissenschaften}}, volume = {6}, pages = {838}, month = oct, year = {2022} }

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Cited by

[1] Tobias Haug and Lorenzo Piroli, “Quantifying Nonstabilizerness of Matrix Product States”, arXiv:2207.13076.

[2] Tobias Haug and M. S. Kim, “Scalable measures of magic for quantum computers”, arXiv:2204.10061.

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