7 Tools to be considered in DFT Flow for IoT Device Design

Gartner says that more than 6.4 billion Internet of Things (IoT) devices will be in use in 2016, and that number will grow to more than 20 billion by 2026, there is no doubt about the importance of IoT-enabled products for this market.

For the semiconductor industry, three factors are crucial when it comes to IoT platforms: a viable business model, reliable device design, and testability of these devices in the coming years. With the emergence of IoT and design of devices for the market, one of the biggest challenges for the manufacturers and integrators in designing IoT enabled products with low power designs and costing, would be to apply design-for-testability (DFT) methodology at the board level for efficient performance in the required area needed to fit within the device.

Major Complexities in IoT Design are:

• IoT Device Data volume checks at less interval of time: Each IoT device has its own hardware and may have different variants of software. It becomes difficult to test all the possible combinations of huge number of data volume under less test time at a low cost.
• IoT Device Faulty Behavior in deployment: In the IoT deployment, prevalent research analyzed that it is becoming complex in testing fault behavior in various elements including: i) Lower geometry nodes, ii) Sensor iii) Connectivity, and iv) Power consumption.
• Smart Memory chip design for IoT Device: It is one of the critical considerations in IoT applications. To meet the need of next-gen products, memory is moving up a level: traditional 8-bit flash memory to embedded flash memory to ultra-low-power memory. This growth came up with multiple issues like:
  • Memory consumption needs to be tested thoroughly to know the response of the devices.
  • IoT sensors run-out of memory when they are integrated with multiple signal requests into the device system.
  • Leakage of memory if accurately not monitored during testing.

The below-mentioned sections dive deeper into testability tools to overcome the above-mentioned challenges in producing reliable IoT-enabled devices to achieve ~100% testability by ensuring proper functioning of the IoT design: 1. Scan Insertion:

• Tool Objective
  • SCAN is a DFT design technique used in IC Design to increase the overall testability of a circuit. SCAN insertion architecture helps to test each of the logic elements in the IC irrespective of its position by inserting test vectors to device pins. It also helps to compress SCAN structure by inserting CODEC (Compressor De-Compressor) architecture, which will help to optimize the utilization of device pins for DFT purpose.
• Tool Description
  • Synopsys – DFT Compiler is useful for implementing various DFT methodologies such as SCAN chain insertion, test point insertion, compression insertion, boundary scan insertion and core wrapping. It is useful for multi-level compressor-decompressor architecture implementation, which will be helpful in optimizing test data volume and test time reduction.
  • Tessent – TestKompressis useful for SCAN insertion along with unique on-chip compression technique, which is helpful in optimizing test data volume and test time reduction.

2. ATPG

• Tools Objective
  • ATPG (Automatic Test Pattern Generation) is an automated algorithm programmed method to generate test patterns. The test patterns generated are used to test semiconductor devices in order to identify the cause of failure and segregate faulty devices and good devices based on its response.
• Tools Description
  • Synopsys – TetraMAX ATPG is useful for various fault models and various formats of pattern generation having optimum runtime. It is useful to optimize pattern generation, coverage analysis, and debug.
  • Tessent – FastScan is useful for optimized pattern generation of various fault models like stuck at, transition, multiple detect transitions, timing-aware, and critical path.

3. MBIST

• Tools Objective
  • MBIST (Memory Built in Self-Test) is logically implemented within the chip to test memory. Because of the decreasing area and increasing complexity in memory, probability of the presence of manufacturing defect increases, testing memories in a chip is very critical.
• Tools Description
  • Synopsys – SMS is a comprehensive, integrated test, repair and diagnostics solution that supports repairable or non-repairable embedded memories across foundries, process node and memory IP vendors. Its highly automated design implementation and diagnostic flow enables System-on-Chip (SoC) designers to achieve quick design closure and significantly improve time-to-market and time-to-yield in volume production. For More Information, Click Here
  • Tessent – MBIST provides a complete solution for at-speed testing, diagnosis, and repair of embedded memory. The solution’s architecture is hierarchical, allowing BIST and self-repair capabilities to be added to individual cores as well as at the top level. It includes a unique comprehensive automation flow that provides design rule checking, test planning, integration, and verification all at the RTL or gate level. For More Information, Click Here

4. Boundary Scan and JTAG

• Tools Objective
  • Boundary scan is a method or architecture for testing interconnects (wire lines) on sub-blocks inside an Integrated Circuit (IC) or printed circuit boards. Boundary scan architecture is helpful in debugging sub block and its interface.
• Tools Description
  • Synopsys-Design Compiler (DFT Compiler) has boundary scan insertion feature.

5. Logical Equivalence

• Tools Objective
  • Logical Equivalence check tools help to verify the design intended functionality remains the same before and after insertion of DFT architecture such as MBIST, SCAN and Boundary SCAN etc.
• Tools Description
  • Synopsys Formality is useful for functional logical equivalence-checking (EC) for subsequent iteration of the design along with ECO cycle implementation.
  • Cadence Conformal is useful for functional logical equivalence-checking (EC) for subsequent iteration of the design with minimal run time.

6. GLS

• Tools Objective
  • GLS (Gate Level Simulation) is used to verify DFT architecture by performing simulation of ATPG patterns. It will help to identify if any discrepancy present in the MBIST, SCAN, and Boundary SCAN architectures.
• Tools Description
  • Synopsys VCS is useful for test pattern simulation with optimum performance having minimal run time.
  • Cadence Xcelium is useful for test pattern simulation with improved performance and having minimal run time with multi-core.

7. Visual Debug

• Tools Objective
  • Visual Debug is the method widely used across the semiconductor industry to analyze the failures identified during GLS. It enhances the debugging capabilities of DFT engineer by visually analyzing signal values on failing logic elements/nodes.
• Tools Description
  • Synopsys -Verdi is useful for design signal visual analysis by loading signal waveform dump and debugging the design signal connectivity in schematic by loading netlist for complex design.
  • Cadence -SimVision is interactiveenvironment useful for design signal visual analysis and netlist schematic view analysis.

When DFT engineers challenge the need for testability and its complexity in IoT device design, there are number of questions that need to be answered.

• Why do we need accuracy in next-gen product deployment?
• Why do we need testability in IoT functionalities?
• How to implement efficient lower geometry node design to achieve faster time to market?

For better understanding and assistance on above mentioned questions and overall testability issues of the circuits that are likely to occur in your chip’s  DFT process, connect with eInfochips team. eInfochips has worked on above-mentioned tools through various tier-1 product based client organizations and has vast experience in it.
Would you like to learn more about how eInfochips help clients in DFT-DFM Architecture for IoT Devices? Get in touch with us.

Co-Author:

Komal Chauhan